VLSI (Very Large Scale Integration) and ULSI (Ultra Large Scale Integration) structures continue to grow in the number of individual devices which are fabricated as part of the integrated circuit, while simultaneously the device geometry is reduced, resulting in not only the reduction of the area covered by the device, but also a reduction in the thickness of the top silicon film. Known prior art electrostatic discharge (ESD) devices which are formed on the top silicon film layer are constructed as lateral devices. As a result, the active area of such ESD protected devices is reduced, resulting in poor ESD protection. In the case where the ESD protection devices are fabricated onto the substrate of the SOI wafer, the process is complicated and takes longer, which means that it costs more to fabricate such a device.